1. Field of the Invention
The present invention relates to a method and apparatus for driving a plasma display panel used for displaying images in a television set or a computer monitor, and more particularly, to a method and apparatus for driving a plasma display panel in which a reset discharge is selectively performed with regard to the distribution of wall charges in discharge cells.
2. Description of the Related Art
Panel driving timing can be divided into a reset (initialization) period, an address period, a sustain period and an erasing period. During the reset period, the state of each cell is initialized for smooth cell addressing. During the address period, cells to be turned on and cells not to be turned on are selected from a panel and wall charges are accumulated at the cells to be turned on. During the sustain period, a discharge is generated in addressed cells to actually display an image. During the erasing period, wall charges of cells are reduced to terminate a sustain discharge.
Contrast is an important factor affecting the quality of an image produced by a plasma display panel. Contrast is represented by the ratio of the brightness of a bright portion to the brightness of a dark portion in a picture displayed on a panel. The bright portion mainly comes from light generated by a sustain discharge, and the dark portion comes from light generated by a reset discharge. Contrast is enhanced by either increasing the brightness of the bright portion or decreasing the brightness of the dark portion.
FIG. 1 is a perspective view of a part of an AC plasma display panel. Pairs of a scan electrode 4 and a sustain electrode 5 which are covered with a dielectric layer 2 and a protective layer 3 are formed to be parallel to one another on a first glass substrate 1. A plurality of address electrodes 8 covered with an insulator layer 7 are formed on a second glass substrate 6. Partition walls 9 are formed on the insulator layer 7 to be parallel to the address electrodes 8. A phosphor layer 10 is formed on the surface of the insulator layer 7 and both sides of the partition walls 9. The first glass substrate 1 and the second glass substrate 6 are disposed to face each other with a discharge space 11 therebetween so that the scan electrodes 4 and the sustain electrodes 5 are orthogonal to the address electrodes 8. The discharge space 11 at an intersection between each address electrode 8 and each pair of a scan electrode 4 and a sustain electrode 5 forms a discharge cell 12.
FIG. 2 is a diagram of an electrode array in a panel. Electrodes form a matrix having m columns and n rows. Address electrodes A1 through Am are arrayed in columns. Scan electrodes SCN1 through SCNn and sustain electrodes SUS1 through SUSn are arrayed in rows. A discharge cell shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
FIG. 3 is a timing chart of driving waveforms according to a conventional method of driving a panel. In this driving method, one frame period is composed of 8 subfields for a 256 gray scale. Each subfield is composed of a reset period, an address period, a sustain period, and an erasing period. Operations in a first subfield will now be described below.
During an early stage of a reset period, all address electrodes A1 through Am and all sustain electrodes SUS1 through SUSn are maintained at 0 V. A ramp voltage signal is applied to all scan electrodes SCN1 through SCNn. The ramp voltage starts from a voltage Vp, which is no greater than a discharge start voltage with respect to the sustain electrodes SUS1 through SUSn, and is slowly increased toward a voltage Vr, which is greater than the discharge start voltage. While the ramp voltage is increasing, a first faint reset discharge occurs from a scan electrode toward an address electrode and a sustain electrode in all discharge cells. As a result, negative wall charges are accumulated on the surface of a protective layer on each scan electrode. Simultaneously, positive wall charges are accumulated on the surface of an insulator layer on each address electrode and the surface of the protective layer on each sustain electrode.
During the latter stage of the reset period, all the sustain electrodes SUS1 through SUSn are maintained at a constant voltage Vh. The ramp voltage is varied to all scan electrodes SCN1 through SCNn starting from a voltage Vq, which is no greater than a discharge start voltage with respect to the sustain electrodes SUS1 through SUSn, and is slowly decreased toward a 0 voltage greater than the discharge start voltage. While the ramp voltage is decreasing, a second faint reset discharge occurs from a sustain electrode toward a scan electrode in all the discharge cells. As a result, the negative wall charge of the surface of the protective layer on each scan electrode and the positive wall charge of the surface of the protective layer on each sustain electrode are decreased. In addition, a faint discharge occurs between an address electrode and a scan electrode, and the positive wall charge of the surface of the insulator layer on each address electrode is adjusted to a value suitable for addressing operation. With such an arrangement, a reset operation is completed during the reset period.
Next, during an address period, all scan electrodes SCN1 through SCNn are maintained at a voltage Vs. A positive address pulse voltage +Vw is applied to a predetermined address electrode Aj (j is an integer between 1 and m) corresponding to a discharge cell to be displayed on a first row, and simultaneously, a scan pulse voltage of 0 V is applied to the scan electrode SCN1 on the first row. Here, a voltage between the surface of the insulator layer and the surface of the protective layer on the scan electrode SCN1, at the intersection between the address electrode Aj and the scan electrode SCN1, is the sum of the address pulse voltage +Vw and the positive wall voltage of the surface of the insulator layer on each address electrode. As a result, an address discharge occurs between the predetermined address electrode Aj and the scan electrode SCN1 and between the sustain electrode SUS1 and the scan electrode SCN1, at the above intersection. Accordingly, at the intersection, a positive wall charge is accumulated on the surface of the protective layer on the scan electrode SCN1, a negative wall charge is accumulated on the surface of the protective layer on the sustain electrode SUS1, and a negative wall charge is accumulated on the surface of the insulator layer on the address electrode Aj.
A sustain period follows the address period. During the sustain period, all the scan electrodes SCN1 through SCNn and all the sustain electrodes SUS1 through SUSn are maintained at 0 V, and then a positive sustain pulse voltage +Vm is applied to all the scan electrodes SCN1 through SCNn. Here, a voltage between the surface of the protective layer on the scan electrode SCNi (i is an integer between 1 and n) and the surface of the protective layer on each sustain electrode, in a discharge cell in which an address discharge has occurred, is the sum of a sustain pulse voltage, a positive wall charge accumulated on the surface of the protective layer on the scan electrode SCN1 during the address period, and a negative wall charge accumulated on the surface of the protective layer on the sustain electrode SUS1 during the address period, which is greater than a discharge start voltage. As a result, a sustain discharge occurs between a scan electrode and a sustain electrode in a discharge cell in which the address discharge has occurred. In the discharge cell in which the sustain discharge has occurred, a negative wall voltage is accumulated on the surface of the protective layer on the scan electrode, and a positive wall voltage is accumulated on the surface of the protective layer on the sustain electrode. Thereafter, the sustain pulse voltage applied to the scan electrode becomes 0 V. Subsequently, a positive sustain pulse voltage +Vm is applied to all the sustain electrodes SUS1 through SUSn, and through the same procedure as described above, a sustain discharge occurs between a scan electrode and a sustain electrode in a discharge cell in which the address discharge has occurred. Thereafter, through the same method as described above, a positive sustain pulse voltage is alternately applied to all scan electrodes SCN1 through SCNn and all the sustain electrodes SUS1 through SUSn, thereby performing a sustain discharge. Such a sustain discharge excites phosphor, thereby generating visible light rays used for displaying an image.
After the sustain period ends, during an erasing period, a ramp voltage starting from 0 V and increasing toward a voltage +Ve is applied to all the sustain electrodes SUS1 through SUSn. Here, in a discharge cell in which a sustain discharge has occurred, a voltage between the surface of the protective layer on a scan electrode and the surface of the protective layer on a sustain electrode is the sum of a negative wall charge on the protective layer on the scan electrode at the last point of the sustain period, a positive wall charge on the protective layer on the sustain electrode at the last point of the sustain period, and the ramp voltage. As a result, a weak erasing discharge occurs between the sustain electrode and the scan electrode in the discharge cell in which the sustain discharge has occurred. In addition, the negative wall charge on the protective layer on the scan electrode and the positive wall charge on the protective layer on the sustain electrode decrease, thereby stopping the sustain discharge. With such arrangement, an erasing operation is completed.
According to conventional technology, a dark portion on a plasma display panel comes from light generated by a reset discharge. When such a reset discharge starts for a single subfield, the reset discharge occurs in all cells. Accordingly, the reset discharge occurs and generates light even in discharge cells which are supposed to be already turned off, thereby reducing contrast.